1. Field
Embodiments described herein relate generally to a verification apparatus for a semiconductor integrated circuit, a verification method for a semiconductor integrated circuit, and a program therefore.
2. Background Art
According to prior art, if sub-banking of a memory is performed, a logic simulation needs to be performed for logic verification. In particular, in the case of a large-scale integrated circuit, gate level simulation takes a very long time, so that even resister transfer level (RTL) simulation needs to be performed. Even after the RTL simulation, a series of design operations including logic synthesis and test circuit insertion takes a long time.
Therefore, it is not practical to perform sub-banking of a memory after logic simulation and logic verification.